1. Field of the Invention
The present invention relates to a charge transfer memory integrated on a semiconductor chip and having a read-in chain of first and second charge transfer elements alternately arranged behind one another and controllable by way of clock pulse lines, with memory and transfer electrodes, and a field of parallel chains of charge transfer elements into which charges characterizing information can be taken over either only from the first or only from the second charge transfer elements of the read-in chain, and having a read-out chain constructed in the same manner as the read-in chain.
2. Description of the Prior Art
Charge transfer memories constructed in a so-called compressed serial-parallel-serial technique, are described, for example, in the German published application No. 2,551,797 or, respectively, the German published application No. 2,518,017, and comprise a serially arranged read-in chain of charge transfer elements, a parallel chain of charge transfer elements allocated to each memory electrode of the serial chain, and of a further serially arranged read-out chain.
By means of such an organization, a very high bit density can be achieved.
As can be seen from the above-mentioned German published applications, the clock pulse program for controlling the memory organizing such a manner is relatively complicated. Inasmuch as information is contained only under each second memory electrode, the serial chain must be read-in twice and the information must be transferred into the parallel field twice. Upon transfer, the information resides under the odd-numbered memory electrodes the first time and under the even-numbered memory electrodes the second time. Therefore, the second transfer must occur displaced by a shift clock pulse. This means that the transfer clock pulses do not arrive at equal intervals, but rather are somewhat displaced with respect to one another. The generation of such non-periodic transfer clock pulses, however, is quite expensive in toto.
In order to create a charge transfer memory in the compressed serial-parallel-serial organization having high bit density which can be controlled in a simple and cost-effective manner with a strictly periodic clock pulse program, it has been proposed to allocate a group of at least two neighboring parallel chains of charge transfer elements provided with receiving or, respectively, delivery electrodes to each first or second charge transfer element of the read-in and read-out chains.
By means of such a memory organization, the charge defining the information is always transferred from the same memory electrodes of the read-in chain and is alternately input into two neighboring parallel chains or, respectively, is always delivered into the same memory electrode of the read-out chain from two neighboring parallel chains.
Charge transfer memories having the specified organizational form can, like all such charge transfer memories, be constructed as two-phase charge transfer memories or as four-phase charge transfer memories. It is likewise possible to actuate four-phase charge transfer memories in two-phase operation. The considerations undertaken in the following hold true for a four-phase charge transfer memory which, for example, is actuated in two-phase operation, a manner of operating in which each second electrode (memory electrode) is driven at the same time as the neighboring electrode (shift electrode). Thereby, an element is defined as a charge transfer element which is composed of memory and shift electrodes.
In previously known charge transfer memories in serial-parallel-serial organization, and constructed in the double silicon technique, the four clock pulses of the serial chains were all supplied from the exterior of the memory field. Such a construction requires a great deal of space on the chip and per period of a serial chain, two contacts are required to a respective additional metal path, namely one of polysilicon-1 (memory electrode) and one of polysilicon-2 (shift electrode).
The charge transferring channel was constricted in the manner of a bottle neck at the cross over from the serial chain into the parallel field and vice versa in the compressed serial-parallel-serial memory modules.
Such constrictions can detrimentally increase the charge losses. Moreover, this location determines the grid dimension and, therefore, the packing density of the serial chains.